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TMP512 bảng dữ liệu(PDF) 38 Page - Texas Instruments

tên linh kiện TMP512
Giải thích chi tiết về linh kiện  Temperature and Power Supply System Monitors
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TMP512 bảng dữ liệu(HTML) 38 Page - Texas Instruments

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TMP512
TMP513
SBOS491A
– JUNE 2010 – REVISED MAY 2011
www.ti.com
Bit Descriptions (continued)
RM3:
Remote Temperature 3 Over-Limit (TMP513 only)
Bit 7
This bit is set to '1' when the result in the Remote Temperature Result 3 Register (0Bh) exceeds the level set in the
Remote Temperature Limit 3 Register (14h) plus half of the temperature hysteresis. It sets also if during conversion
of remote channel 3 an open diode condition was detected. It clears in transparent mode when the result in the
Remote Temperature Result 3Register (0Bh) is below the level set in the Remote Temperature Limit 3 Register
(14h) minus half of the temperature hysteresis and the last conversion of channel 3 was done without open-diode
detection.
CVR:
Conversion Ready
Bit 6
The Conversion Ready line is provided to help coordinate one-shot conversions for shunt voltage, bus voltage,
current and power measurements. The Conversion bit is set after all conversions, averaging, and multiplication
events are complete. Conversion Ready clears under the following conditions:
1.
Writing to the One-Shot bit in Configuration Register 1.
2.
Reading the Status Register.
CRT:
Conversion Ready Temperature
Bit 5
The Conversion Ready Temperature line is provided to help coordinate one-shot conversions for local and remote
temperature measurements. The Conversion bit is set after all enabled channels complete the respective
conversions. Conversion Ready Temperature clears under the following conditions:
1.
Writing to the One-Shot bit in Configuration Register 1.
2.
Reading the Status Register.
PVLD:
Power Valid Error
Bit 4
In latch mode, this bit is set to '1' when the brown-out detect fires during a conversion. The flag sets to '1' at the
conversion end. It clears by reading the Status Register.
SMBA:
SMBus Alert
Bit 3
This bit is set when the Alert pin is active. When in latch mode, it clears only on reading the Status Register,
disabling the SMBus Alert function, or using SMBus Alert Response. In transparent mode, it clears when the
triggering condition is not present.
OVF:
Math Overflow
Bit 2
This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data
may be meaningless. It does not set the Alert pin.
38
Copyright
© 2010–2011, Texas Instruments Incorporated



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