TMP117MAIDRVT datasheet(27/50 Pages) TI2

27 / 50 page

7.6.3 Configuration Register (address = 01h) [factory default reset = 0220h]

Return to Register Map.

Figure 7-14. Configuration Register

HIGH_Alert

LOW_Alert

Data_Ready

EEPROM_Busy

MOD1(2)

MOD0(1)

CONV2(1)

CONV1(1)

R-0

R/W-0

R/W-1

R/W-0

CONV0(1)

AVG1(1)

AVG0(1)

T/nA(1)

POL(1)

DR/Alert(1)

Soft_Reset

—

R/W-0

R/W-1

R/W-0

R-0

Table 7-6. Configuration Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

HIGH_Alert

High Alert flag:

1: Set when the conversion result is higher than the high limit

0: Cleared on read of configuration register

Therm mode:

1: Set when the conversion result is higher than the therm limit

0: Cleared when the conversion result is lower than the

hysteresis

LOW_Alert

Low Alert flag:

1: Set when the conversion result is lower than the low limit

0: Cleared when the configuration register is read

Therm mode: Always set to 0

Data_Ready

Data ready flag.

This flag indicates that the conversion is complete and the

temperature register can be read. Every time the temperature

bit is set at the end of the conversion when the temperature

pin by setting bit 2 of the configuration register.

EEPROM_Busy

EEPROM busy flag.

The value of the flag indicates that the EEPROM is busy during

programming or power-up.

11:10

MOD[1:0]

R/W

Set conversion mode.

00: Continuous conversion (CC)

01: Shutdown (SD)

10: Continuous conversion (CC), Same as 00 (reads back = 00)

11: One-shot conversion (OS)

9:7

CONV[2:0]

R/W

100

Conversion cycle bit.

See Table 7-7 for the standby time between conversions.

6:5

AVG[1:0]

R/W

Conversion averaging modes. Determines the number of

conversion results that are collected and averaged before

updating the temperature register. The average is an

accumulated average and not a running average.

00: No averaging

01: 8 Averaged conversions

10: 32 averaged conversions

11: 64 averaged conversions

T/nA

R/W

Therm/alert mode select.

1: Therm mode

0: Alert mode

POL

R/W

ALERT pin polarity bit.

1: Active high

0: Active low

DR/Alert

R/W

ALERT pin select bit.

1: ALERT pin reflects the status of the data ready flag

0: ALERT pin reflects the status of the alert flags

www.ti.com

TMP117

SNOSD82D – JUNE 2018 – REVISED SEPTEMBER 2022

Submit Document Feedback

Product Folder Links: TMP117

TMP117MAIDRVT bảng dữ liệu(PDF) 27 Page - Texas Instruments

TMP117MAIDRVT bảng dữ liệu(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bảng dữ liệu tải về

Link URL