6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1) (2)

MIN

MAX

UNIT

Voltage

VIN (for legacy chip only)

–0.3

24

V

VIN (for new chip only)

–0.3

30

Voltage

VOUT (for legacy chip only)

–0.3

5.0

V

Voltage

VOUT (for fixed output new chip only)

–0.3

2 × VOUT(typ)

or VIN + 0.3

or 5.5

(whichever is

lower)

V

Current

Peak output current

Internally limited

Temperature

Junction, TJ

–40

150

°C

Storage, Tstg

–65

150

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2)

All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)

±2000

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN

NOM

MAX

UNIT

VIN

Input supply voltage

2.5

24

V

VOUT

Output voltage

1.205

5

V

IOUT

Output current

0

150

mA

CIN

Input capacitor(2)

0

0.047

µF

COUT

Output capacitor (for legacy chip only)

0.47

1

Output capacitor (for new chip only) (3)

1

TJ

Operating junction temperature

-40

125

°C

(1)

All voltages are with respect to GND.

(2)

An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.047 μF is

recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system

level instability such as ringing or oscillation, especially in the presence of load transients.

(3)

All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 0.47 μF

minimum for the stability.

TLV701

SBVS161A – NOVEMBER 2011 – REVISED APRIL 2023

www.ti.com

4

Submit Document Feedback

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TLV701