TDP2004 datasheet(9/34 Pages) TI2

9 / 34 page

5.6 High Speed Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Channel to channel xtalk (between

adjacent active channels, FEXT

Minimum over 50.0MHz to 10.0Ghz

range, normalized to EQ gain of 0dB

–38

LINEARITY-

Output DC linearity

1650

mVpp

LINEARITY-

Output AC linearity at GAIN = L4

8Gbps

1250

mVpp

LINEARITY-

Output AC linearity at GAIN = L4

16Gbps

1200

mVpp

LINEARITY-

Output AC linearity at GAIN = L4

20Gbps

1100

mVpp

5.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Target Mode

tSP

Pulse width of spikes which must be

suppressed by the input filter

tHD-STA

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

0.6

µs

tLOW

LOW period of the SCL clock

1.3

µs

THIGH

HIGH period of the SCL clock

0.6

µs

tSU-STA

Setup time for a repeated START

condition

0.6

µs

tHD-DAT

Data hold time

µs

TSU-DAT

Data setup time

0.1

µs

Rise time of both SDA and SCL

signals

Pullup resistor = 4.7kΩ, Cb = 10pF

120

Fall time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF

tSU-STO

Setup time for STOP condition

0.6

µs

tBUF

Bus free time between a STOP and

START condition

1.3

µs

tVD-DAT

Data valid time

0.9

µs

tVD-ACK

Data valid acknowledge time

0.9

µs

Capacitive load for each bus line

400

Controller Mode

fSCL-M

SCL clock frequency

303

kHz

tLOW-M

SCL low period

1.90

µs

THIGH-M

SCL high period

1.40

µs

tSU-STA-M

Setup time for a repeated START

condition

µs

tHD-STA-M

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

1.5

µs

TSU-DAT-M

Data setup time

1.4

µs

tHD-DAT-M

Data hold time

0.5

µs

tR-M

Rise time of both SDA and SCL

signals

Pullup resistor = 4.7kΩ, Cb = 10pF

120

www.ti.com

TDP2004-Q1

SNLS787 – SEPTEMBER 2025

Submit Document Feedback

Product Folder Links: TDP2004-Q1

TDP2004 bảng dữ liệu(PDF) 9 Page - Texas Instruments

TDP2004 bảng dữ liệu(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL