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TAS5548 bảng dữ liệu(PDF) 28 Page - Texas Instruments |
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TAS5548 bảng dữ liệu(HTML) 28 Page - Texas Instruments |
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28 / 118 page ![]() PWM+ PWM- PWM+ PWM- > 0 Idle Center of Negative Signal) < 0 PWM + PWM - offset (Center of Positive Signal) PWM+ PWM– Differential Voltage TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 www.ti.com Figure 21. BD Modulation Figure 22. Ternary Modulation 7.4.9 TAS5548 DAP Architecture Diagrams The TAS5548 defaults to processing audio data (post ASRC) at double rate. In the TAS5548, this is set to 96kHz (by the external XTAL used). . Additional support is provided for native 192kHz support. 4ch of audio processing is available in 192kHz native processing mode. Figure 23 shows the TAS5548 DAP architecture for fS ≤ 96 kHz. The bass management architecture is shown in channels 1, 2, 7 and 8. The I2C registers are shown to help the designer configure the device. Figure 24 shows the architecture for fS = 176.4 kHz or fS = 192 kHz. Note that only channels 1, 2, 7 and 8 contain limited features. Channels 3–6 are pass-through except for volume controls. Figure 25 shows TAS5548 detailed channel processing. The output mixer is 8×2 for channels 1–6 and 8×3 for channels 7 and 8. 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 |
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