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IS25LE01G-RILA3 bảng dữ liệu(PDF) 164 Page - Integrated Silicon Solution, Inc

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Giải thích chi tiết về linh kiện  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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nhà sản xuất  ISSI [Integrated Silicon Solution, Inc]
Trang chủ  http://www.issi.com
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IS25LE01G-RILA3 bảng dữ liệu(HTML) 164 Page - Integrated Silicon Solution, Inc

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Rev. A6
01/14/2025
8.63 GANG SECTOR/BLOCK LOCK OPERATION (GBLK, 7Eh)
The Gang Sector/Block Lock (GBLK) instruction provides a quick method to set all DYB (Dynamic Protection Bit)
bits to “0” at once.
Before the GBLK (7Eh) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The sequence of issuing GBLK instruction is: drive CE# low → send GBLK instruction code → drive CE# high.
The instruction code will be shifted into the device on the rising edge of SCK.
The GBLK command is accepted in both SPI and QPI mode. The CE# must go high exactly at the byte boundary,
otherwise, the instruction will be ignored. While the GBLK operation is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the GBLK operation, and is “0” when
it is completed.
Figure 8.138 Gang Sector/Block Lock Sequence In SPI Mode
Instruction = 7Eh
CE#
SCK
SI
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SO
High Impedance
Figure 8.139 Gang Sector/Block Lock Sequence In QPI Mode
7Eh
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0



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