IS25LE01G-RILA3 datasheet(89/186 Pages) ISSI

tên linh kiện	IS25LE01G-RILA3

Giải thích chi tiết về linh kiện	SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

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IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

01/14/2025

8.13 SECTOR ERASE OPERATION (SER, D7h/20h or 4SER, 21h)

A Sector Erase (SER/4SER) instruction erases a 4 Kbyte sector before the execution of a SER/4SER instruction,

the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically

reset after the completion of Sector Erase operation.

• D7h/20h (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• D7h/20h (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• 21h is followed by a 4-byte address (A31-A0)

A SER/4SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire

instruction sequence The SER/4SER instruction code, and three or four address bytes as above are input via SI.

Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the

erase voltage and timing.

The progress or completion of the erase operation can be determined by reading the WIP bit. If the WIP bit is “1”,

the e

rase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed.

Figure 8.27 Sector Erase Sequence In SPI Mode (D7h/20h [EXTADD=0], 3-byte address)

Instruction = D7h/20h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

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