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IS25LE01G-RILA3-TY bảng dữ liệu(PDF) 39 Page - Integrated Silicon Solution, Inc

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Giải thích chi tiết về linh kiện  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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nhà sản xuất  ISSI [Integrated Silicon Solution, Inc]
Trang chủ  http://www.issi.com
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IS25LE01G-RILA3-TY bảng dữ liệu(HTML) 39 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
39
Rev. A6
01/14/2025
6.7 ECC REGISTER
Related Commands: Read ECC Register (RDECC B3h), Write ECC Register (WRECC B5h), Clear ECC Register
(CLECC, B6h).
Table 6.26 ECC Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
IPA_ECCB
ECCCOUNTER
ECCEVENT
ECCONOFF
Default
0
0
0
0
0
0
0
0
Table 6.27 ECC Register Bit Definition
Bit
Name
Definition
Read-
/Write
Type
0
ECCONOFF
ECC ON/OFF bit:
"0" indicates ECC is ON (default)
"1" indicates ECC is OFF
R/W
Volatile
1
ECCEVENT
ECC Event bit:
"0" indicates NO ECC correction event (default)
"1" indicates YES ECC correction event
R
Volatile
5:2
ECCCOUNTER
Store cumulative ECC correction occurrence.
Max. 15 ECC correction occurrence can be stored, and stays 15
after further occurrence.
“0000” is the default value.
R
Volatile
6
IPA_ECCB
Incremental Programming Attempt within ECC boundary bit:
“0” indicates NO IPA within ECC Boundary (default)
“1” indicates YES IPA with ECC Boundary.
Incremental Programming within ECC boundary is not allowed, and
automatically ignored when ECC is ON.
R
Volatile
7
Reserved
Reserved
R
Reserved



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