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UCC28700DBVT bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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UCC28700DBVT bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 36 page ![]() UCC28700, UCC28701, UCC28702, UCC28703 www.ti.com SLUSB41A – JULY 2012 – REVISED DECEMBER 2014 Device Functional Modes (continued) Figure 12. Simplified Flyback Convertor (with the main voltage regulation blocks) In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer energy to the secondary. As shown in Figure 13 it is clear there is a down slope representing a decreasing total rectifier VF and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.05 V; the resistor divider is selected as outlined in the VS pin description. Figure 13. Auxiliary Winding Voltage The UCC28700 VS signal sampler includes signal discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 14 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, TLK_RESET in Figure 14. Because this can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time less than 500 ns for IPRI minimum, and less than 1.5 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following TLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary winding voltage by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2) / RS2. Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: UCC28700 UCC28701 UCC28702 UCC28703 |
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