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ICS853052AG REV. B OCTOBER 24, 2007

ICS853052

DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER

PRELIMINARY

This section provides information on power dissipation and junction temperature for the ICS853052.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

CC

= 5.5V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

MAX

= V

CC_MAX

* I

EE_MAX

= 5.5V * 21mA = 115.5mW

MAX

= 30.94mW/Loaded Output pair

2.

Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS

The equation for Tj is as follows: Tj =

θ

Tj = Junction Temperature

θ

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θ

flow and a multi-layer board, the appropriate value is 112.7°C/W per Table 6B below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.146W * 112.7°C/W = 101.52°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθθθθ

JA

FOR

θθθθθ

JA

by Velocity (Meters per Second)

01

2

Multi-Layer PCB, JEDEC Standard Test Boards

101.7°C/W

90.5°C/W

89.8°C/W

θθθθθ

JA

by Velocity (Linear Feet per Minute)

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

153.3°C/W

128.5°C/W

115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

112.7°C/W

103.3°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

θθθθθ

JA

FOR