ICS844071 datasheet(8/15 Pages) IDT

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ICS844071

FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR

IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS844071AG SEPTEMBER 26, 2007

Parameter Measurement Information, continued

Differential Output Voltage Setup

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. The ICS44071 provides separate

power supplies to isolate any high switching noise from the outputs

to the internal PLL. VDD and VDDA should be individually

connected to the power supply plane through vias, and bypass

capacitors should be used for each pin. To achieve optimum jitter

performance, power supply isolation is required. Figure 1

illustrates how a 10

Ω resistor along with a 10µF and a 0.01µF

bypass capacitor should be connected to each VDDA pin.

Figure 1. Power Supply Filtering

➤

100

out

LVDS

DC Input

VOD/∆ VOD

VDD

VDDA

3.3V or 2.5V

Ω

10µF

.01µF

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