SN75DP130SSRGZRG4 datasheet(21/55 Pages) TI2

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SN75DP130

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SLLSE57E – APRIL 2011 – REVISED MARCH 2015

9.3.5 Link Training and DPCD

The SN75DP130 monitors the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers

during Link Training in DP mode to select the output voltage swing VOD, output pre-emphasis, and the EQ setting

of the Main Link. The AUX monitor for SN75DP130 supports Link Training in 1Mbps Manchester mode, and is

disabled during TMDS mode (CAD_SNK=VIH).

The AUX channel is further monitored for the DisplayPort D3 standby command.

The DPCD registers monitored by SN75DP130 are listed in Figure 17. Bit fields not listed are reserved and

values written to reserved fields are ignored.

Figure 17. DPCD Registers Used by the SN75DP130 AUX Monitor

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. DPCD Registers Used by the SN75DP130 AUX Monitor

Address

Field

Type

Description

Bits 7:0 = Link Bandwidth Setting

Write Values:

06h – 1.62 Gbps per lane

0Ah – 2.7 Gbps per lane (default)

14h – 5.4 Gbps per lane

00100h

LINK_BW_SET

Note: any other value is reserved; the SN75DP130 will revert to 5.4 Gbps

operation when any other value is written

Read Values:

00h – 1.62 Gbps per lane

01h – 2.7 Gbps per lane (default)

02h – 5.4 Gbps per lane

Bits 4:0 = Lane Count

Write Values:

00h – All lanes disabled (default)

01h – One lane enabled

02h – Two lanes enabled

04h – Four lanes enabled

00101h

LANE_COUNT_SET

Note: any other value is invalid and disables all Main Link output lanes

Read Values:

00h – All lanes disabled (default)

01h – One lane enabled

03h – Two lanes enabled

0Fh – Four lanes enabled

Write Values:

Bits 1:0 = Output Voltage VOD Level

00 – Voltage swing level 0 (default)

01 – Voltage swing level 1

10 – Voltage swing level 2

11 – Voltage swing level 3

Bits 4:3 = Pre-emphasis Level

00 – Pre-emphasis level 0 (default)

01 – Pre-emphasis level 1

10 – Pre-emphasis level 2

11 – Pre-emphasis level 3

Note: the following combinations are not allowed for bits [1:0]/[4:3]: 01/11, 10/10,

00103h

TRAINING_LANE0_SET

10/11, 11/01, 11/10, 11/11; setting to any of these invalid combinations disables

all Main Link lanes until the register value is changed back to a valid entry

Read Values:

Bits 1:0 = Output Voltage VOD Level

00 – Voltage swing level 0 (default)

01 – Voltage swing level 1

10 – Voltage swing level 2

11 – Voltage swing level 3

Bits 3:2 = Pre-emphasis Level

00 – Pre-emphasis level 0 (default)

01 – Pre-emphasis level 1

10 – Pre-emphasis level 2

11 – Pre-emphasis level 3

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