5.9 Driver Switching Characterisitics

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tpLH

Propagation delay time, low-to-

high-level output

See Figure 6-5

1.3

1.9

2.4

ns

tpHL

Propagation delay time, high-to-

low-level output

1.3

1.9

2.4

ns

tr

Differential output signal rise time

0.9

2

ns

tf

Differential output signal fall time

0.9

2.2

ns

tsk(o)

Output skew

200

ps

tsk(p)

Pulse skew (|tPHL – tPLH|)

150

ps

tsk(pp)

Part-to-part skew (2)

300

ps

tjit(per)

Period jitter, rms (1 standard

deviation)(3)

All channels switching, 125 MHz

clock input(4), see Figure 6-8

2

ps

tjit(c-c)

Cycle-to-cycle jitter, rms(3)

9

ps

tjit(det)

Deterministic jitter(3)

All channels switching, 250 Mbps

215–1 PRBS input(4), see Figure 6-8

290

ps

tjit(r)

Random jitter(3)

4

ps

tPZH

Enable time, high-impedance-to-

high-level output

See Figure 6-6

7

ns

tPZL

Enable time, high-impedance-to-

low-level output

7

ns

tPHZ

Disable time, high-level-to-high-

impedance output

7

ns

tPLZ

Disable time, low-level-to-high-

impedance output

7

ns

(1)

All typical values are at 25°C and with a 3.3-V supply voltage.

(2)

tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3)

Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4)

tr = tf = 0.5 ns (10% to 90%)

SN65MLVD040

SLLS902A – FEBRUARY 2010 – REVISED MARCH 2024

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