SNx4LVC02A Quadruple 2-Input Positive-NOR Gates

1 Features

• Operate from 1.65V to 3.6V

• Specified from –40°C to 85°C,

–40°C to 125°C, and –55°C to 125°C

• Inputs accept voltages to 5.5V

• Max tpd of 4.4ns at 3.3V

• Typical VOLP (output ground bounce)

<0.8V at VCC = 3.3V, TA = 25°C

• Typical VOHV (output VOH undershoot)

>2V at VCC = 3.3V, TA = 25°C

• Latch-up performance exceeds 250mA per JESD

17

2 Description

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

The device performs the Boolean function Y = A + B

or Y = A

⋅ B in positive logic.

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of this device as a

translator in a mixed 3.3V/5V system environment.

Device Information

PART NUMBER

PACKAGE SIZE(1)

PACKAGE SIZE(2)

BODY SIZE(3)

SNx4LVC02A

BQA (WQFN, 14)

3mm × 2.5mm

3mm × 2.5mm

D (SOIC, 14)

8.65mm × 6mm

8.65mm × 3.9mm

DB (SSOP, 14)

6.2mm × 7.8mm

6.2mm × 5.3mm

NS (SOP, 14)

10.2mm × 7.8mm

10.3mm × 5.3mm

PW (TSSOP, 14)

5mm × 6.4mm

5mm × 4.4mm

RGY (VQFN, 14)

3.5mm × 3.5mm

3.5mm × 3.5mm

FK (LCCC, 20)

8.9mm x 8.9mm

8.89mm × 8.89mm

J (CDIP, 14)

19.55mm x 7.9mm 19.55mm x 6.7mm

W (CFP, 14)

9.21mm x 9mm

9.21mm x 6.28mm

(1)

For more information, see Section 10.

(2)

The package size (length × width) is a nominal value and

includes pins, where applicable.

(3)

The body size (length × width) is a nominal value and does

not include pins.

Logic Diagram, Each Gate (Positive Logic)

SN54LVC02A, SN74LVC02A

SCAS280T – JANUARY 1993 – REVISED DECEMBER 2024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.