L99LD01 datasheet(36/69 Pages) STMICROELECTRONICS

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SPI functional description

L99LD01

36/69

DocID025319 Rev 3

3Fh clears all status registers simultaneously and reads back the configuration register

(GLOBCTR).

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The

command byte allows to determine which register content is read then erased while the data

byte is ‘don’t care’.

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the

falling edge of the serial clock (SCK). The first byte corresponds to the Global Status byte

and the second to the content of the addressed register.

In order to avoid inconsistency between the Global status byte and the status register, the

status register contents are frozen during SPI communication.

Figure 25. SPI read and clear operation

Read device information

Specific information can be read but not modified during this mode.

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The

command byte allows to determine which information is read while the data byte is ‘don’t

care’.

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the

falling edge of the serial clock (SCK). The first byte corresponds to the Global Status byte

and the second to the content of the addressed register.

CSN

SDO

SDI

MSB

LSB

Command Byte

Global Status Byte

(8 bit)

Data

(8 bit)

Don’t care

(8 bit)

1LSB

Address

MSB

L99LD01 bảng dữ liệu(PDF) 36 Page - STMicroelectronics