ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER

SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2

ICS308

REV J 120507

Pin Assignment

Pin Descriptions

16

1

15

2

14

DA T A

S T RO B E

3

13

X2

4

12

X1/IC LK

SC LK

5

11

CLK 9

6

PD T S

7

VD D

8

GN D

VD D

VD D

GN D

CLK 1

CLK 5

CLK 2

CLK 6

9

10

CLK 3

CLK 7

CLK 4

CLK 8

20

19

18

17

20 pin (150 m il) SSOP (QSOP)

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

DATA

Input

Serial data input.

2

X2

XO

Crystal Output. Connect this pin to a crystal. Float for clock input.

3

X1/ICLK

XI

Connect this pin to a crystal or external clock input.

4

CLK9

Output

Output clock 9. Default of Reference frequency output when unprogrammed.

5

VDD

Power

Connect to +3.3 V.

6

GND

Power

Connect to Ground.

7

CLK1

Output

Output clock 1. Default of Reference frequency output when unprogrammed.

8

CLK2

Output

Output clock 2. Default of Reference frequency output when unprogrammed.

9

CLK3

Output

Output clock 3. Default of Reference frequency output when unprogrammed.

10

CLK4

Output

Output clock 4. Default of Reference frequency output when unprogrammed.

11

CLK8

Output

Output clock 8. Default of Reference frequency output when unprogrammed.

12

CLK7

Output

Output clock 7. Default of Reference frequency output when unprogrammed.

13

CLK6

Output

Output clock 6. Default of Reference frequency output when unprogrammed.

14

CLK5

Output

Output clock 5. Default of Reference frequency output when unprogrammed.

15

GND

Power

Connect to Ground.

16

VDD

Power

Connect to +3.3 V.

17

VDD

Power

Connect to +3.3 V.

18

PDTS

Input

Powers down entire chip, tri-states all outputs when low. Internal pull-up.

19

SCLK

Input

Serial Shift register clock. See timing diagram.

20

STROBE

Input

Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.