6 Detailed Description

6.1 Overview

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of

the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

changing data at D does not affecting the levels at the outputs.

6.2 Functional Block Diagram

Figure 6-1. Logic Diagram (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table (each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H1

H1

H

H

↑

H

H

L

H

H

↑

L

L

H

H

H

L

X

Q0

Q 0

1. This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive

(high) level.

SN54ACT74, SN74ACT74

SCAS520J – AUGUST 1995 – REVISED APRIL 2025

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