M41T00CAP

Clock operation

3.5

Oscillator fail detection

If the oscillator fail bit (OF) is internally set to '1,' this indicates that the oscillator has either

stopped, or was stopped for some period of time and can be used to judge the validity of

the clock and date data. In the event the OF bit is found to be set to '1' at any time other

than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately

reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to

be set:

•

The first time power is applied (defaults to a '1' on power-up).

•

The voltage present on VCC is insufficient to support oscillation.

•

The ST bit is set to '1'.

•

External interference of the crystal.

The OF bit will remain set to '1' until written to logic '0.' The oscillator must have started and

run for at least 4 seconds before attempting to reset the OF bit to '0.'

3.6

Output driver pin

When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the

contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT

bit) of address location 07h are '0's, then the FT/OUT pin will be driven low.

The FT/OUT pin is an open drain which requires an external pull-up resistor.

3.7

Initial power-on default

Upon initial application of power to the device, the OUT and FT bits will be in the '0' state,

and the ST and OF bits will be in the '1' state. All other register bits will initially power on in

random states (see Table 3: "Preferred default values").

Table 3: Preferred default values

Condition

ST

OUT

FT

OF

Initial power-up

(1)

1

0

0

1

Subsequent power-up (with battery backup)

(2)

UC

UC

0

UC

Notes:

(1)

State of other control bits undefined.

(2)

UC = unchanged

DocID014557 Rev 6

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