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M41ST85WMH6E bảng dữ liệu(PDF) 28 Page - STMicroelectronics

tên linh kiện M41ST85WMH6E
Giải thích chi tiết về linh kiện  3.0/3.3 V I²C combination serial RTC, NVRAM supervisor and microprocessor supervisor
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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M41ST85WMH6E bảng dữ liệu(HTML) 28 Page - STMicroelectronics

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Clock operation
M41ST85W
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DocID7531 Rev 12
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.13
trec bit
Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic
continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling
time before WRITEs may again be performed to the device after a power-down condition.
The trec bit will allow the user to set the length of this deselect time as defined by Table .
3.14
Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state:
watchdog register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state:
ST, OUT, and HT (see Table ).
Table 6. trec definitions
trec bit (TR)
STOP bit (ST)
trec time
Units
Min
Max
0
0
96
98
ms
0
1
40
200(1)
1. Default setting
ms
1
X
50
2000
µs
Table 7. Default values
Condition
TR
ST
HT
Out
FT
AFE
ABE
SQWE
Watchdog
register(1)
1. WDS, BMB0-BMB4, RB0, RB1.
Initial power-up(2)
2. State of other control bits undefined.
0
1
1
1
0
0
0
0
0
Subsequent power-up
(with battery backup)(3)
3. UC = Unchanged
UC
UC
1
UC
0
0
0
0
0



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