L99MH98 datasheet(49/147 Pages) STMICROELECTRONICS

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Table 33. SPI ERROR bit

MSB

Description

No SPI error in previous access and no RESET event before this access

SPI error in previous access or RESET event before this access

6.3.2.2

Global Status Bit (GSBN)

The GSBN is a logically NOR combination of DSR1 and DSR2 registers + SPI error bit + RSTB bit + WDG error

bit. GSBN bit is directly related to the DIAGN pin.

•

GSBN = 1 (no error), DSR1 bits + DSR2 bits + SPI error bit + RSBT bit all set to 0

•

GSBN = 0 (error), one or more bit/s of DSR1 or DSR2 or SPI error or RSBT is/are set to 1

6.3.2.3

Address

The Address bits are used to indicate the register on which the operation has been performed:

•

In case of SPI error or reset or first access, address field contains the address of the DRS0 register

•

In other cases, both for read and write, Address field contains the address selected in the previous frame

6.3.2.4

Data word

The payload (Data Byte 2 to Data Byte 1) is the data transferred to the device with every SPI communication, and

always follows the Address bits indicating:

•

In case of SPI error or reset or first access, data field contains the DRS0 register data saved at CS falling

•

In other cases, both for read and write, data field contains the data value of the register at the address

selected saved at CS falling

6.3.3

Protocol failure detection

To achieve a communication protocol that covers certain fail-safe requirements a basic set of SPI communication

failure detection mechanisms are implemented.

6.3.3.1

Clock count

During communication (CSN low) a clock monitor counts the valid CLK clock edges. The number of rising edges

of a valid communication command must be 24. If the number of rising edges is not 24 the SPI write command

will be ignored and the SPI error bit will be set in the response of the next SPI command.

6.3.3.2

CLK polarity (CPOL) check

During the falling and rising edge of CS the level of SCLK must be low. If SCLK is not low during the falling or the

rising edge of CS, the SPI write command will be ignored and the SPI error bit will be set in the response of the

next SPI command.

6.3.3.3

CSN timeout

By pulling CSN low the SDO is set active and leaves its tristate condition. To ensure communication between

other SPI devices within the same bus even in case of CSN stuck at low a CSN timeout is implemented. By

pulling CSN low an internal timer is started. When the timer reaches its end, the ongoing command is rejected,

the SPIE is set (and it will be visible at the next communication) and the SDO is set in tristate condition.

6.3.3.4

SDI stuck at LOW

As a communication with data all ‘0’ and OpCode ‘0’ on address b’000000’ cannot be distinguished between a

valid command and a SDI stuck at LOW, this communication is not allowed. Nevertheless, in case a stuck at LOW

is detected the command will be rejected and the SPIE will be set and it will be visible at the next communication.

6.3.3.5

SDI stuck at HIGH

As a communication with data all ‘1’ and OpCode ‘1’ on address b’111111’ cannot be distinguished between a

valid command and a SDI stuck at HIGH, this communication is not allowed. In case a stuck at HIGH is detected

the command will be rejected and the SPIE will be set and it will be visible at the next communication.

L99MH98

Serial peripheral interface (SPI)

DS14611 - Rev 3

page 49/147

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