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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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IS25LE512M-RMLA3:P-TY bảng dữ liệu(PDF) 31 Page - Integrated Silicon Solution, Inc |
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IS25LE512M-RMLA3:P-TY bảng dữ liệu(HTML) 31 Page - Integrated Silicon Solution, Inc |
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31 / 189 page  IS25LE512M IS25WE512M Integrated Silicon Solution, Inc.- www.issi.com 31 Rev. A6 06/16/2025 1.8V Device (IS25WE) P[6:3] Dummy Cycles2,3 Fast Read5 0Bh/0Ch Fast Read5 0Bh/0Ch Fast Read Dual Output 3Bh/3Ch Fast Read Dual IO BBh/BCh Fast Read Quad Output 6Bh/6Ch Fast Read Quad IO EBh/ECh FRDTR 0Dh/0Eh FRDDTR BDh/BEh FRQDTR EDh/EEh SPI QPI SPI SPI SPI SPI, QPI SPI/QPI SPI4 SPI, QPI 0 Default1 112MHz 75MHz 112MHz 84MHz 112MHz 75MHz 66/66MHz 60MHz 66MHz 1 1 66MHz 25MHz 66MHz 33MHz 50MHz 25MHz 50/11MHz 29MHz 11MHz 2 2 84MHz 33MHz 84MHz 50MHz 66MHz 33MHz 63/23MHz 40MHz 23MHz 3 3 104MHz 40MHz 104MHz 66MHz 75MHz 40MHz 66/34MHz 52MHz 34MHz 4 4 110MHz 50MHz 110MHz 84MHz 84MHz 50MHz 66/46MHz 60MHz 46MHz 5 5 112MHz 66MHz 112MHz 90MHz 95MHz 66MHz 66/58MHz 66MHz 58MHz 6 6 112MHz 75MHz 112MHz 104MHz 104MHz 75MHz 66/66MHz 66MHz 66MHz 7 7 112MHz 84MHz 112MHz 108MHz 110MHz 84MHz 66/66MHz 66MHz 66MHz 8 8 112MHz 93MHz 112MHz 112MHz 112MHz 93MHz 66/66MHz 66MHz 66MHz 9 9 112MHz 104MHz 112MHz 112MHz 112MHz 104MHz 66/66MHz 66MHz 66MHz 10 10 112MHz 110MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz 11 11 112MHz 112MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz 12 12 112MHz 112MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz 13 13 112MHz 112MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz 14 14 112MHz 112MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz 15 15 112MHz 112MHz 112MHz 112MHz 112MHz 112MHz 66/66MHz 66MHz 66MHz Notes: 1. Default dummy cycles are as follows. Operation Command Dummy Cycles Comment SPI mode QPI mode SPI mode QPI mode Fast Read 0Bh/0Ch 0Bh/0Ch 8 6 RDUID, IRRD instructions are also applied. Fast Read Dual Output 3Bh/3Ch - 8 - Fast Read Quad Output 6Bh/6Ch - 8 - Fast Read Dual IO BBh/BCh - 4 - Fast Read Quad IO EBh/ECh EBh/ECh 6 6 Fast Read DTR 0Dh/0Eh 0Dh/0Eh 8 6 Fast Read Dual IO DTR BDh/BEh - 4 - Fast Read Quad IO DTR EDh/EEh EDh/EEh 6 6 2. Enough number of dummy cycles must be applied to execute properly the AX read operation. 3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X must be Hi-Z. 4. QPI mode is not available for FRDDTR command. 5. RDUID, IRRD instructions are also applied. |
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