MSP430F412IPM datasheet(12/66 Pages) TI2

12 / 66 page

MSP430x41x

MIXED SIGNAL MICROCONTROLLER

SLAS340J − MAY 2001 − REVISED DECEMBER 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple software access

is provided with this arrangement.

interrupt enable 1 and 2

654

OFIE

WDTIE

rw-0

Address

ACCVIE

NMIIE

rw-0

654

Address

BTIE

rw-0

WDTIE:

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is

configured in interval timer mode.

OFIE:

Oscillator fault interrupt enable

NMIIE:

Nonmaskable interrupt enable

ACCVIE:

Flash access violation interrupt enable

BTIE:

Basic Timer1 interrupt enable

interrupt flag register 1 and 2

654

OFIFG

WDTIFG

rw-0

rw-1

rw-(0)

Address

02h

NMIIFG

654

Address

BTIFG

rw-0

WDTIFG:

Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,

or a reset condition at the RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

NMIIFG:

Set via RST/NMI pin

BTIFG:

Basic Timer1 interrupt flag

module enable registers 1 and 2

654

Address

04h/05h

Legend: rw−0,1:

Bit Can Be Read and Written. It Is Reset or Set by PUC.

rw−(0,1):

Bit Can Be Read and Written. It Is Reset or Set by POR.

SFR Bit Not Present in Device.

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