11 Power Supply Recommendations

There are no power sequence requirements for the LSF Family. Refer to Section 10.2.1.1.1 for enabling and

reference voltage guidelines.

12 Layout

12.1 Layout Guidelines

The signal integrity is highly related with pull-up resistor and PCB capacitance condition because LSF Family is

switch-type level translator

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.

• Place LSF close to high voltage side.

• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

12.2 Layout Example

GND

Vref_A

EN

Vref_B

A1

A2

B1

B2

LSF0102

Short Signal Trace as possible

Minimize Stub as possible

1

2

3

4

5

6

7

8

Figure 12-1. Short Trace Layout

SDIO Connector

(3.3V IO)

SD Controller

(1.8V IO)

LSF0108

SDIO level translator

Device PCB

TP1

TP2

Figure 12-2. Device Placement

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LSF0204, LSF0204D

SLVSCP5H – JULY 2014 – REVISED APRIL 2021

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Product Folder Links: LSF0204 LSF0204D