LP5569RTWRG4 datasheet(49/93 Pages) TI2

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LP5569

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SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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8.6.1.15 LED2_PWM Register (Address = 18h) [reset = 0h]

LED2_PWM is shown in Figure 41 and described in Table 30.

Return to Summary Table.

LED2 PWM Register

This is the PWM duty cycle control for the LED2 output.

Figure 41. LED2_PWM Register

pwm2

R/W-0h

Table 30. LED2_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm2

R/W

00h = 0% duty cycle (default)

...

80h = 50% duty cycle

...

FFh = 100% duty cycle-

8.6.1.16 LED3_PWM Register (Address = 19h) [reset = 0h]

LED3_PWM is shown in Figure 42 and described in Table 31.

Return to Summary Table.

LED3 PWM Register

This is the PWM duty cycle control for the LED3 output.

Figure 42. LED3_PWM Register

pwm3

R/W-0h

Table 31. LED3_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm3

R/W

00h = 0% duty cycle (default)

...

80h = 50% duty cycle

...

FFh = 100% duty cycle

8.6.1.17 LED4_PWM Register (Address = 1Ah) [reset = 0h]

LED4_PWM is shown in Figure 43 and described in Table 32.

Return to Summary Table.

LED4 PWM Register

This is the PWM duty cycle control for the LED4 output.

Figure 43. LED4_PWM Register

pwm4

R/W-0h

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