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M41TC8025AMC7F bảng dữ liệu(PDF) 21 Page - STMicroelectronics |
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21 / 41 page ![]() DocID022873 Rev 4 21/41 M41TC8025 Operation 2.6.4 Starting the fixed-cycle timer interrupt The fixed-cycle timer interrupt internal counter value starts at the rising edge of the SCL signal that occurs when the TE value is changed from "0" to "1" (after the LSB is transferred). Refer to Figure 11 for a detailed illustration. Figure 11. Fixed-cycle timer interrupt starting point 2.6.5 Stopping the fixed-cycle timer interrupt When the RESET bit in control register 0Fh is 1, the clock divider <4 KHz is stopped. As a result, the fixed-cycle timer interrupt with source clocks of 64 Hz, 1 Hz and "minute" update will be stopped. The RESET bit will not affect the fixed-cycle timer interrupt with the source clock of 4,096 Hz. 2.6.6 Example operation of the fixed-cycle timer interrupt The fixed-cycle timer interrupt example is given in Figure 12. The fixed-cycle timer interrupt timing sequence is given in Figure 13. Figure 12. Example of fixed-cycle timer interrupt Obsolete Product(s) - Obsolete Product(s) |
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