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M41T93 bảng dữ liệu(PDF) 27 Page - STMicroelectronics |
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M41T93 bảng dữ liệu(HTML) 27 Page - STMicroelectronics |
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27 / 56 page ![]() DocID12615 Rev 8 27/56 M41T93 Clock operation 56 The on-chip capacitance can be calculated as follows: CLOAD = 12.5 + [ACS:(AC6:AC0 value, decimal)] ● 0.125 pF where ACS is the sign. Examples: ACAL (addr 12h) = 0 ➔ CLOAD = 12.5 pF ACAL = 10111100b ➔ CLOAD = 5 pF ACAL = 00010100b ➔ CLOAD = 15 pF With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of 3.5 pF load capacitance as shown on the bottom row of Table 5. Note: These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the analog calibration register value. Any invalid value of analog calibration will result in the default capacitance of 25 pF (for CXI and CXO). Combining the digital adjustment range (–63 to +126 ppm) and analog adjustment range (–15 to +95 ppm), the approximate overall adjustment range of the M41T93’s timekeeping is –78 to +221 ppm. Figure 12 represents a typical curve of clock ppm adjustment versus the analog calibration value. Actual crystals may vary, so users should evaluate the crystals to be used with an M41T93 device before establishing the adjustment values for a given application. |
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