MP2236C

– 18V, 6A, FCCM SYNCHRONOUS STEP-DOWN CONVERTER

MP2236C Rev. 1.0

MonolithicPower.com

12

3/16/2022

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© 2022 MPS. All Rights Reserved.

OPERATION

The

MP2236C

is

a

fully

integrated,

synchronous, rectified, step-down, switch-mode

converter. The device uses constant-on-time

(COT) control to provide fast transient response

and ease loop stabilization. Figure 2 shows the

simplified ramp compensation block in the

MP2236C.

VOUT

L

COUT

RESR

R1

R2

On-

Timer

Logic

Control

VREF

SW

VRAMP

FB

Figure 2: Simplified Compensation Block

At the beginning of each cycle, the high-side

MOSFET (HS-FET) turns on whenever the

ramp voltage (VRAMP) is below the error amplifier

(EA)’s output voltage (VEAO), which indicates an

insufficient output voltage (VOUT). The on period

is determined by both VOUT and the input

voltage (VIN) to make the switching frequency

(fSW) fairly constant across the entire VIN range.

After the on period elapses, the HS-FET turns

off. By cycling the HS-FET on and off, the

converter regulates VOUT. The integrated low-

side MOSFET (LS-FET) turns on when the HS-

FET is off to minimize conduction loss.

If the HS-FET and LS-FET are turned on at the

same time, a dead short occurs between the

input and GND; this is called shoot-through. To

avoid

significantly

reduced

efficiency

from

shoot-through, the MP2236C generates a dead

time (DT) internally between the HS-FET off

period and LS-FET on period, and vice versa.

Error Amplifier (EA)

The EA compares the FB voltage (VFB) against

the internal 0.6V reference voltage (VREF) and

outputs a pulse-width modulation (PWM) signal.

The optimized internal ramp compensation

minimizes the external component count and

simplifies control loop design.

Enable (EN)

EN is a digital control pin that turns the

regulator on and off. Pull EN high to turn on the

regulator. Pull EN low to turn off the regulator.

An internal 2M

Ω resistor is connected from EN

to ground. EN can operate with a 20V VIN,

which allows EN to be connected directly to VIN

for automatic start-up.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating with

an insufficient supply

voltage. The MP2236C

’s UVLO comparator

monitors VIN. The MP2236C is active when VIN

exceeds the UVLO rising threshold.

Soft Start (SS) and Pre-Biased Start-Up

Soft start (SS) prevents the converter

’s VOUT

from overshooting during start-up. When the

chip starts up, the internal circuitry generates a

soft-start voltage (VSS) that ramps up from 0V to

the internal VCC. When VSS is below VREF, the

EA uses VSS as the reference. When VSS

exceeds VREF, VREF takes over as the reference.

The soft-start time (tSS) is set to 1ms internally.

If

the MP2236C’s output is pre-biased to a

certain voltage during start-up, the IC disables

the HS-FET and LS-FET switching until the

voltage on the internal SS capacitor (CSS)

exceeds the sensed VOUT at FB.

Low-Dropout (LDO) Operation

To improve dropout, the MP2236C is designed

to extend its on time if the duty cycle exceeds

85%. When the HS-FET on time is extended,

the frequency drops. The typical minimum

frequency

(fSW_MIN)

is

260kHz.

When

the

frequency drops to 260kHz, it cannot reduce

any further and the HS-FET off time begins

decreasing.

The

duty

cycle

reaches

its

maximum (DMAX) when the off time is at its

minimum value. If VIN drops, the MP2236C

operates at DMAX and VOUT drops.

The typical DMAX can be calculated using

Equation (1):

MAX

OFF_MIN

SW _ MIN

D

1 t

f

= −



(1)

Where the minimum off time (tOFF_MIN) is 170ns,

and fSW_MIN is 260kHz.