STA680TR datasheet(25/48 Pages) STMICROELECTRONICS

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DS5877 Rev 13

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STA680

Operation and general remarks

3.2

Power on

This chapter describes the power-on procedure for the cold start (i.e. when the device is not

supplied before being turned on). Figure 7 and Table 4 show the timing for the cold start

power up sequence.

Boot pins are latched at startup. Their default value is logic 0, in case logic 1 is needed a

6K2 pull-up resistor should be connected on the corresponding boot line. After reset

release, the boot selection lines become outputs.

Figure 7. Power on timing

1. In case the Reference Clock is fed through BB1_BCK or CLK_IN the Power On timing diagram is the same as

Figure 7 where OSC_OUT is substituted by the external supplied stable reference clock.

Figure 8. Crystal characteristics

Table 4. Power on timing parameters

Symbol

Parameter

Min

Max

Unit

Tramp-up

External supply ramp-up time

Same ramp-up time for

3.3 V and 1.2 V supply

TDC1V8

DC1V8 regulator start-up time

TOSC (1)

1. The oscillator start-up time depends on the crystal connected to the internal oscillator. The given value is

estimated for a crystal with characteristic shown in Figure 8.

Oscillator start-up time

400

μs

TRST

Reset release time

TCFG,S

Setup time for clock configuration

0.1

μs

TCFG,H

Hold time for clock configuration

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