AB-RTC-TNA-32.768kHz-2

Ultra-Low Power RTC Module

Revision: Initial Release

9/9/2025

Page 5

Disclaimer

lign

Check Inventory

S

lign

Request Samples

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Inputs

VIH

HIGH level input voltage

VDD = 1.5 V to 5.5 V Pins: SCL,

SDA, CLKOE, EVI

0.8 * VDD

V

VIL

LOW level input voltage

0.2 * VDD

V

ILEAK

Input leakage current

VSS ≤ VI ≤ VDD

TA= -40°C to +105°C

-0.5

0.5

µA

CI

Input capacitance

VDD = 3.0 V, TA = 25°C,

f = 1 MHz

7

pF

Outputs

VOH:CLK

HIGH level output voltage

CLKOUT

VDD = 1.5 V, IOH = 0.1 mA

1.2

V

VDD = 3.0 V, IOH = 1.0 mA

2.5

VDD = 5.0 V, IOH = 1.0 mA

4.5

VOL:CLK

LOW level output voltage

CLKOUT

VDD = 1.5 V, IOH = -0.1 mA

0.2

V

VDD = 3.0 V, IOH = -1.0 mA

0.5

VDD = 5.0 V, IOH = -1.0 mA

0.5

TCKH

CLKOUT enable time(7)

FCLKOUT = 32.768kHz

0

30.5

µs

TCKL

CLKOUT disable time(7)

0

µs

VOL

LOW level output voltage

Pins: SDA, INT

VDD = 1.5 V, IOH = -2.0 mA

-

0.4

V

VDD = 3.0 V, IOH = -3.0 mA

0.4

VDD = 5.0 V, IOH = -3.0 mA

0.3

IOLEAK

Output leakage current

Vo =VDD or VSS, TA=-40°C to

+105°C

-0.5

0.5

µA

COUT

Output capacitance

VDD = 3.0 V, TA = 25°C,

f = 1 MHz

7

pF

DC Characteristics (TA = -40 to +85°C unless otherwise indicated. VDD = 1.5 to 5.5V, fOSC=32.768kHz, TYP values at 25°C and

3.0V)

Note 1:

See also VDD Backup and recovery AC Electrical Characteristics and Parameters in section BACKUP AND RECOVERY.

Note 2:

Clocks operating and RAM and registers retained. Including temperature sensing and compensation.

Note 3:

CLKOUT is held LOW during power on delay tPOR1 and is HIGH during the power on reset duration tPOR2.

Note that between VLOW1 (1.2 V) and VDD MIN (1.5 V), time accuracy specification limits are not guaranteed.

Note 4:

All inputs and outputs are at 0 V or VDD.

Note 5:

2.2k pull-up resistors on SCL/SDA, excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are

at 0 V or VDD. Test conditions: Continuous burst read/write, 55h data pattern, 25 μs between each data byte, 20 pF load on each bus pin.

Note 6:

When CLKOUT is enabled (CLKOE is HIGH) the additional VDD supply current ΔIVDD can be calculated as follows: ΔIVDD = CL x VDD x fOUT, e.g.

ΔIVDD = 10 pF x 3.0 V x 32’768 Hz = 980 nA ≈ 1 μA

Note 7:

Also refer to section 32.768 KHZ ENABLE/DISABLE TIMING.