LM76005RNPR datasheet(36/51 Pages) TI2

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10.1.2 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

the area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck

converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,

and then return to the ground of the input capacitors, as shown in Figure 10-1.

PVIN

PGND

OUT

High di/dt current

BUCK

CONVERTER

Figure 10-1. Buck Converter High di / dt Path

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor or capacitors as close as possible to the PVIN and PGND

pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible, and just

wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes)

must be used for high current conduction path to minimize parasitic resistance. The output capacitors must be

placed close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the

bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to

PGND and the exposed PAD.

10.1.3 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are

connected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input

and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load

variations. The PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground

plane. The other side of the ground plane contains much less noise — use for sensitive routes.

Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a

minimum 4 x 4 array of 10-mil thermal vias to connect the PAD to the system ground plane for heat sinking.

Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the top

and bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copper

thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough

copper thickness and proper layout provides low current conduction impedance, proper shielding and lower

thermal resistance.

The thermal characteristics of the LM76005 are specified using the parameter RθJA, which characterize the

junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device.

To obtain an estimate of the device junction temperature, you can use the following relationship:

TJ = PD × RθJA + TA

(28)

where

• TJ = junction temperature in °C

• PD = VIN × IIN × (1 − efficiency) − (1.1 × (IOUT)2× DCR)

• DCR = inductor DC parasitic resistance in Ω

LM76005

SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020

www.ti.com

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