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LM46002PWPRG4 bảng dữ liệu(PDF) 43 Page - Texas Instruments |
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LM46002PWPRG4 bảng dữ liệu(HTML) 43 Page - Texas Instruments |
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43 / 54 page ![]() AGND 1 2 3 4 5 6 8 7 10 VIN COUT VOUT CBIAS RFBT RFBB CFF L GND CVCC GND SW CBOOT VCC BIAS SYNC RT PGOOD SW VIN PGND EN SS/TRK FB PGND VIN GND VOUT sense PAD (17) CIN 16 9 15 14 13 12 11 Place bypass caps close to pins Ground bypass caps to DAP As much copper area as possible, for better thermal performance Preferably use GND Plane as a middle layer for shielding and heat dissipation Preferably place and route on top layer and use solid copper on bottom layer for heat dissipation VOUT sense point is away from inductor and past COUT As much copper area as possible, for better thermal performance VOUT distribution point is away from inductor and past COUT Route VOUT sense trace away from SW and VIN nodes. Preferably shielded in an alternative layer CBOOT Place CBOOT close to pins GND Place ceramic bypass caps close to VIN and PGND pins Place RFBB close to FB and AGND Trace to FB short and thin 43 LM46002 www.ti.com SNVSA13C – APRIL 2014 – REVISED APRIL 2019 Product Folder Links: LM46002 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated 10.2 Layout Example Figure 102. LM46002 PCB Layout Example and Guidelines |
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