LM13700

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SNOSBW2F – NOVEMBER 1999 – REVISED NOVEMBER 2015

System Examples (continued)

Figure 37. Zero Stand-By Power Timer

The operation of the multiplexer of Figure 38 is very straightforward. When A1 is turned on it holds VO equal to

VIN1 and when A2 is supplied with bias current then it controls VO. CC and RC serve to stabilize the unity-gain

configuration of amplifiers A1 and A2. The maximum clock rate is limited to about 200 kHz by the LM13700 slew

rate into 150 pF when the (VIN1–VIN2) differential is at its maximum allowable value of 5 V.

The Phase-Locked Loop of Figure 39 uses the four-quadrant multiplier of Figure 24 and the VCO of Figure 36 to

produce a PLL with a ±5% hold-in range and an input sensitivity of about 300 mV.

Figure 38. Multiplexer

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