TDA7479

Output timing

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Output timing

The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According

to the internal PLL lock condition data change can result on the falling or on the rising clock edge

(see Figure 3). Whichever clock edge is used by the decoder (rising or falling edge) the data will

remain valid for 416.7 µs after the clock transition.

Figure 3.

RDS timing diagram

RDCL

RDDA

CLOCK

LINE

DATA

LINE

4.3µs

td

4.3µs

837.7µs

421µs

421µs