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DP83867IRPAPR bảng dữ liệu(PDF) 13 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer Transceiver
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6.5 Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing the device.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
PAP
P1000
Power consumption, 2
supplies (1) (2)
530
mW
P1000
Power consumption, optional
3rd supply(1) (2)
490
mW
IDD25
Supply Current, 2 supplies
141
mA
IDD11
125
mA
IDDIO (1.8V)
22
mA
IDD25
Supply Current, optional 3rd
supply
90
mA
IDD11
125
mA
IDD18
51
mA
IDDIO (1.8V)
19
mA
RGZ
P1000
Power consumption, 2
supplies (1) (2)
495
mW
P1000
Power consumption, optional
3rd supply(1) (2)
457
mW
IDD25
Supply Current, 2 supplies
137
mA
IDD10
108
mA
IDDIO (1.8V)
24
mA
IDD25
Supply Current, optional 3rd
supply
86
mA
IDD10
108
mA
IDD18
50
mA
IDDIO (1.8V)
24
mA
(1)
Power consumption represents total operational power for 1000BASE-T.
(2)
See Section 8.3 for details on 2-supply and 3-supply configuration.
(3)
Specified by production test, characterization, or design.
6.6 Power-Up Timing
See Figure 6-1.
PARAMETER
TEST CONDITIONS (1)
MIN
NOM
MAX UNIT
T1
Post power-up stabilization time prior to MDC
preamble for register accesses
MDIO is pulled high for 32-bit serial
management initialization.
200
ms
T2
Hardware configuration latch-in time from
power up
Hardware Configuration Pins are
described in Section 7.5.1.
200
ms
T3
Hardware configuration pins transition to
output drivers
64
ns
(1)
Specified by production test, characterization, or design.
www.ti.com
DP83867IR, DP83867CR
SNLS484I – FEBRUARY 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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