 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
DP83867IRPAP bảng dữ liệu(PDF) 39 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DP83867IRPAP bảng dữ liệu(HTML) 39 Page - Texas Instruments |
|
|
39 / 139 page  7.4.3.8 Auto-Negotiation Complete Time Parallel detection and Auto-Negotiation typically take 2-3 seconds to complete. In addition, Auto-Negotiation with next page exchange takes approximately 2-3 seconds to complete, depending on the number of next pages exchanged. Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to Auto-Negotiation 7.4.3.9 Auto-MDIX Resolution The DP83867 can determine if a straight or crossover cable is used to connect to the link partner. The PHY can automatically re-assign channel A and B to establish link with the link partner, (and channel C and D in 1000BASE-T mode). Auto-MDIX resolution precedes the actual Auto-Negotiation process that involves exchange of FLPs to advertise capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section 40.8.2. There is no required implementation for 10BASE-Te and 100BASE-TX. DP83867 devices manufactured after August, 2022, have an increased random seed value that now includes 255 different seed values to expedite Auto-MDIX resolution with a link partner. For 10/100, Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX works in both Auto-Negotiation mode and manual forced speed mode. 7.4.4 Loopback Mode There are several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the digital and analog data paths. Generally, the DP83867 can be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. MII Loopback is configured using the BMCR (register address 0x0000). All other loopback modes are enabled using the BISCR (register address 0x16). Except where otherwise noted, loopback modes are supported for all speeds (10/100/1000) and all MAC interfaces (RGMII and GMII). MAC MII Loopback Digital Loopback PCS Loopback Analog Loopback External Loopback Reverse Loopback Figure 7-11. Loopbacks The availability of Loopback depends on the operational mode of the PHY. The Link Status in these loopback modes is also affected by the operational mode. Table 7-3 lists out the availability of Loopback Modes and corresponding Link Status indication. Table 7-3. Loopback Availability LOOPBACK MODE MAC INTERFACE 1000M 100M 10M AVAILABILIT Y LINK STATUS AVAILABILIT Y LINK STATUS AVAILABILIT Y LINK STATUS MII GMII/RGMII Yes No Yes No Yes No PCS GMII/RGMII Yes No Yes Yes No No Digital GMII/RGMII Yes Yes Yes Yes Yes Yes Analog GMII/RGMII Yes Yes Yes Yes Yes Yes External GMII/RGMII No No Yes Yes Yes Yes www.ti.com DP83867IR, DP83867CR SNLS484I – FEBRUARY 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DP83867IR DP83867CR |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
