DP83867CSRGZ datasheet(86/129 Pages) TI2

86 / 129 page

7.6.53 SGMII Control Register 1 (SGMIICTL1)

Table 7-63. SGMII Control Register 1 (SGMIICTL1), Address 0x00D3

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

SGMII_TYPE

0, RW

SGMII Configuration:

1 = 6-wire mode. Enable differential SGMII clock to MAC.

0 = 4-wire mode

13:0

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

7.6.54 Sync FIFO Control (SYNC_FIFO_CTRL)

Table 7-64. Sync FIFO Control (SYNC_FIFO_CTRL), Address 0x00E9

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

RESERVED

0x9F22, RW

RESERVED

7.6.55 Loopback Configuration Register (LOOPCR)

Table 7-65. Loopback Configuration Register (LOOPCR), Address 0x00FE

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

LOOP_CFG_VAL

1110 0111 0010

0001, RW

Loopback Configuration Value:

1110 0111 0010 000: Configuration for loopback modes.

A software reset through bit 14 of the Control Register (CTRL),

address 0x001F, is required after changes to this register value.

Other values for this register are not recommended.

7.6.56 DSP Configuration (DSP_CONFIG)

Table 7-66. DSP Configuration (DSP_CONFIG), Address 0x0100

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

DSP_CONFIG

0x051C, RW

DSP Configuration. Value 0x1027 can further improve the immunity

margins during EMC testing.

7.6.57 DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)

Certain applications can need this register to be configured to 0x0E81 to improve Short Cable performance.

Changing this register to 0x0E81, does not effect Long Cable performance.

Table 7-67. DSP Feedforward Equalizer Configuration (DSP_FFE_CFG), Address 0x012C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:10

RESERVED

0000 11, RO

RESERVED

9:0

FFE_EQ

00 0010 1101,

FFE Equalizer Configuration

Set this field to 10 1000 0001 when using cables of length <= 1m.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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