VNQ6004SATR-E datasheet(21/73 Pages) STMICROELECTRONICS

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VNQ6004SA-E

Functional description

of TCSD can be set using the bits CTDTH1 and CTDTH0 inside the CTLR register (see

Section 3.3.1).

2.2.3

Protections

Junction over temperature

If the junction temperature of one channel rises above the shutdown temperature TTSD, an

over temperature event (OT) is detected. The channel is switched OFF and the

corresponding bit in the over temperature status register OTFLTR (address 30h) is set.

Consequently, the thermal shutdown bit (bit 4) in the Global Status Byte and the Global Error

Flag are set.

Each output channel can be either set in Autorestart or Latched OFF operation in case of

junction over temperature event by setting the corresponding ASDTCR register bit (address

08h).

In Autorestart operation, the output is switched off as described and switches on again

automatically when the junction temperature falls below the reset temperature TR. The

status bit is latched during OFF-state of the channel in order to allow asynchronous

diagnostic and it is automatically cleared when the junction temperature falls below the

thermal reset temperature of OT detection TRS.

In Latched OFF operation, the output remains switched OFF until the junction temperature

falls below TRS and a read and clear command is sent.

Power limitation

If the difference between junction temperature and case temperature (

ΔT = Tj – Tc) rises

above the power limitation threshold

ΔTPLIM, a power limitation event is detected. The

corresponding bit in the power limitation status register PWLMFLTR (address 33h) is set

and the channel is switched OFF. Consequently, the power limitation bit (bit 4) in the Global

Status Byte and the Global Error Flag are set.

Each output channel can be either set in Autorestart or Latched OFF operation in case of

power limitation event by setting the corresponding ASDTCR register bit (address 08h).

In Autorestart operation, the output is switched off as described and switches on again

automatically when

ΔT falls below the reset threshold ΔTPLIMreset. The status bit is latched

during OFF-state of the channel in order to allow asynchronous diagnostic and it is

automatically cleared in ON-state when the power limitation event is removed.

In Latched OFF operation, the output remains switched OFF until

ΔT falls below the reset

threshold

ΔTPLIMreset and a read and clear command is sent.

Each time a channel is switched on via the corresponding bit in SOCR, a blanking time

tblanking is initialized which masks a power limitation event and its relevant diagnostic in the

PWLMFLTR register. The blanking time does not account for an over temperature event, i.e.

the outputs are switched OFF and the relevant bits in OTFLTR are set even during the

blanking time, or for an over load event.

The blanking filter is only active, if the channel is turned on through SOCR. There are,

however, additional conditions which cause the output to switch from OFF to steady

ON-state or to PWM output which do not activate the blanking filter. Refer to Table 6 for

more details.

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