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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TDA7801SM bảng dữ liệu(PDF) 31 Page - STMicroelectronics |
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TDA7801SM bảng dữ liệu(HTML) 31 Page - STMicroelectronics |
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31 / 48 page  DocID022674 Rev 4 31/48 TDA7801 I2S bus interface 7 I2S bus interface The TDA7801 accepts the I2S standard format that could be time division multiplexed (TDM), however the WS still needs a 50% duty-cycle to work correctly. The Figure 34 shows the different I2C settings allowed for the I2S interface (2,4 or 8 channels transmission on a single serial data line (SD) can be selected). By I2C programming it is possible to choose between the following interface settings: a) channel 1 and channel 3 channel on SD1_3 and channel 2 and channel 4 on SD2_4 b) all four channels on SD2_4. SD1_3 has not function. c) eight channels transferred on the SD2_4 line. This setting is feasible in the PowerSO36 and Flexiwatt27 package. Figure 34. TDM setting The TDA7801 accepts the I2S standard format with a bit clock (SCK) equal to 64 fs. Note, TDM setting is guaranteed for a maximum Fs = 96 kHz. Figure 35. I2S format |
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