VN9D5D20F datasheet(53/96 Pages) STMICROELECTRONICS

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5.4

Overload (VDS high voltage, overload (OVL))

During low duty cycle PWM operation on a shorted load, the ON time is normally too short to allow power

limitation or overtemperature detection, and the ADC output does not report the current flowing on the channel. In

this situation, the detection of the overload condition is quite difficult. To overcome this, the voltage drop on the

PowerMOS (VDS) is measured every time the channel is turned OFF. If VDS (voltage across PowerMOS output

stage) exceeds the threshold defined by the parameter VDS_OVL, an overload condition is detected. The

corresponding bit in the overload status register VDSFSR (address from 0x20h to 0x23h depending on the

channel) of the OUTSRx register is set (see the Section 5.11: VDS feedback status register “VDSFSR” in

OUTSRx register).

Consequently, the bit 4 in the Global Status Byte is set if it is not masked in the CONFIG register through the

dedicated “VDSMASK” bit. The VDSFSR is a warning and the channel can be switched on again even if the

VDSFSRx bit is set. The VDSFSRx bit remains unchanged until a read and clear command on VDSFSR is sent

by the SPI or until the output is turned off the next time, when the VDS is evaluated again. In case of low duty

cycle PWM operation (i.e. 3% typical at 200 Hz in Bulb mode), if the output channel is switched ON for a very

short time, VDS might be greater than a threshold defined by the parameter VDS_OVL even if the output is not in

overload state so that a false warning is issued.

Figure 24. Diagnostics flowchart for digital overload detection

GADG1004171611PS

Channel feedback register

Detailed diagnosis in ON state

Evaluate

Power limitation

Overload

Temperature Status

Critical:

OT/PL on

signalled channel

End

No err.

Error bit(s)

set

Overload on

signalled

channel(s)

Please refer to Section 4.3.1: Global status byte description, Section 5.8: CHFBSR: channel feedback status bit in

OUTSRx register and Section 5.11: VDS feedback status register “VDSFSR” in OUTSRx register.

5.5

Open-load ON-state detection

The open-load ON-state is performed by reading the digital current sense. In case the output is on and the

reported digital current sense value is below the requested threshold, the open-load condition can be reported.

5.6

Open-load OFF-state detection

After the channel is completely OFF, if the output voltage Vout exceeds the open detection threshold VOL, an

open-load in OFF state / Stuck to VCC event is reported.

As a consequence, the corresponding bit STKFLTR in the OUTSRx register (address 0x20h to 0x23h) is set, the

OLOFF bit in the global status Register and the global status bit NOT are set accordingly.

VN9D5D20F

Diagnostic

DS12936 - Rev 10

page 53/96

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