PWM

8

7

6

5

4

9

P

GND

1

V

IN

SKIP#

V

SW

V

DD

P

GND

BOOT

BOOT_R

2

3

4

CSD97374Q4M

SLPS382D – JANUARY 2013 – REVISED AUGUST 2016

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Product Folder Links: CSD97374Q4M

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5 Pin Configuration and Functions

SON 3.5 mm × 4.5 mm

Top View

Pin Functions

PIN

DESCRIPTION

NO.

NAME

1

SKIP#

This pin enables the diode emulation function. When this pin is held low, diode emulation mode is enabled for the

sync FET. When SKIP# is high, the CSD97374Q4M operates in forced continuous conduction mode. A tri-state

voltage on SKIP# puts the driver into a very low power state.

2

VDD

Supply voltage to gate drivers and internal circuitry.

3

PGND

Power ground. Needs to be connected to Pin 9 and PCB.

4

VSW

Voltage switching node. Pin connection to the output inductor.

5

VIN

Input voltage pin. Connect input capacitors close to this pin.

6

BOOT_R

Bootstrap capacitor connection. Connect a minimum 0.1-µF 16-V X5R ceramic cap from BOOT to BOOT_R pins. The

bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. Boot_R is

internally connected to VSW.

7

BOOT

8

PWM

Pulse width modulated tri-state input from external controller. Logic low sets control FET gate low and sync FET gate

high. Logic high sets control FET gate high and sync FET gate low. Open or Hi-Z sets both MOSFET gates low if

greater than the tri-state shutdown hold-off time (t3HT).

9

PGND

Power ground.