t

PLH2

t

PLH0

t

PHL0

t

PLH1

t

PHL1

t

PHL2

INP

INN

QP0

QN0

QP1

QN1

QP2

QN2

80%

20%

0 V

t

R

t

F

OUTPx

OUTNx

V

OH

V

OL

V

OUT,DIFF,PP (= 2 x V

)

OD

VOD

LVDS

50 W

Phase Noise

Analyzer

LVDS

100 W

Oscilloscope

7

CDCLVD1213

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SCAS897A – JULY 2010 – REVISED OCTOBER 2016

Product Folder Links: CDCLVD1213

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Copyright © 2010–2016, Texas Instruments Incorporated

7 Parameter Measurement Information

Figure 3. LVDS Output DC Configuration During Device Test

Figure 4. LVDS Output AC Configuration During Device Test

Figure 5. Output Voltage and Rise/Fall Time

(1)

Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn

or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2).

(2)

Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest

tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2).

Figure 6. Output and Part-to-Part Skew