L9663 datasheet(82/106 Pages) STMICROELECTRONICS

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Communication interface

L9663

82/106

DS11401 Rev 6

5.2

SPI interface

5.2.1

Physical layer and signal description

Figure 26. SPI interface

Chip Select (CS)

The communication interface is deselected when this input signal is logically high. A falling

edge on CS enables and starts the communication, while a rising edge finishes the

communication and the command is executed if a valid frame has been sent. During

communication start and stop, the Serial Clock (SCLK) has to be logically low. The MISO

line is in high impedance when CS is high.

In order to considerably reduce the number of CS lines and pins on the system, while still

allowing connecting different devices, an address multiplexing approach is implemented in

the device with cabled address "00".

This means that if CS is low the device is not selected unless the MOSI bits 31 and 30 of the

frame matches the device address.

This feature can be disabled by SW, writing a dedicated SPI bit.

The default state after reset (sw, hw or by internal clock fault) is in the address multiplexing

mode.

Serial Clock (SCLK)

This SCLK provides the clock of the SPI. Data present on the MOSI line is latched on the

falling edge of Serial Clock (SCLK) into the internal shift registers, while data from the

internal shift registers are shifted out on the MISO line on the rising edge.

MOSI

This input is used to transfer data serially into the device. Data is latched on the falling edge

of Serial Clock (SCLK).

μC

SPI Master

L 9663

SPI Slave

SCK

MOSI

MISO

GAPG2710151524PS

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