SN74AHCT240Q1

OCTAL BUFFER/DRIVER

WITH 3STATE OUTPUTS

SCLS582B − APRIL 2004 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Qualified for Automotive Applications

D Inputs Are TTL-Voltage Compatible

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

description/ordering information

This octal buffer/driver is designed specifically to

improve the performance and density of 3-state

memory-address

drivers,

clock

drivers,

and

bus-oriented receivers and transmitters.

The SN74AHCT240 device is organized as two 4-bit

buffers/line drivers with separate output-enable (OE)

inputs. When OE is low, the device passes data from

the A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION{

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74AHCT240IPWRQ1

AHCT240I

† For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

(each 4-bit buffer/driver)

INPUTS

OUTPUT

OE

A

OUTPUT

Y

L

H

L

L

LH

H

X

Z

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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9

10

20

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17

16

15

14

13

12

11

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

VCC

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

PW PACKAGE

(TOP VIEW)