STA326_V01 datasheet(28/64 Pages) STMICROELECTRONICS

28 / 64 page

STA326

28/64

DocID11531 Rev 9

Figure 17. Serial input data timing

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

Table 19. Serial input data timing characteristics (fs = 32 to 192 kHz)

Parameter in Figure 17

Value

BICKI frequency (slave mode)

12.5 MHz max.

BICKI pulse width low (T0) (slave mode)

40 ns min.

BICKI pulse width high (T1) (slave mode)

40 ns min.

BICKI active to LRCKI edge delay (T2)

20 ns min.

BICKI active to LRCKI edge delay (T3)

20 ns min.

SDI valid to BICKI active setup (T4)

20 ns min.

BICKI active to SDI hold time (T5)

20 ns min.

Table 20. Delay serial clock enable

Bit

R/W

RST

Name

Description

DSCKE

Delay serial clock enable:

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 21. Channel input mapping

Bit

R/W

RST

Name

Description

C1IM

0: processing channel 1 receives left I2S input

1: processing channel 1 receives right I2S input

C2IM

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

Obsolete

Product(s)

- Obsolete

Product(s)

STA326 bảng dữ liệu(PDF) 28 Page - STMicroelectronics

STA326 bảng dữ liệu(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

bảng dữ liệu tải về

Link URL