STM32WL33C8V6 datasheet(14/91 Pages) STMICROELECTRONICS

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3.5.3

Linear voltage regulators

The digital power supplies are provided by different regulators:

•

main LDO (MLDO):

–

provides 1.2 V from a 1.4 to 3.6 V input voltage

–

supplies both VDD12i and VDD12o when the device is active

–

is disabled during the low power mode (Deepstop)

•

Low power LDO (LPREG):

–

stays enabled during both active and low power phases

–

provides 1.0 V or 1.2 V voltage selectable by software

–

not connected to the digital domain when the device is active

–

connected to the VDD12o domain during low power mode (Deepstop)

•

Dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block

The embedded SMPS step-down converter is inserted between the external power and the LDOs.

Figure 7. Power supply domains overview

SMPS

LP Reg

Main Reg

RF LDOs

VDDIO

LSI, LSE,

BOR, PVD,

PWR33, RCC33

Always ON

VDD12

MR_SUBGHz_wakeup

LPAWUR, LPUART,

COMP, RTC, IWDG,

LCD, DAC, LCSC,

PWRCo, RCCo

Interruptible

domain

VDD12I

HSI, HSE,

MR_SUBGHz,

LPAWUR,

Peripheral RCCi

Analog RF

VDD

VLX

VFB

3.5.4

Power voltage supervisor

The STM32WL33xx device embeds several power voltage monitoring:

•

Power On reset (POR) / Power Down reset (PDR) / Brown-Out reset (BOR)

•

BORH monitoring

•

Power voltage detector (PVD)

3.6

Operating modes

The STM32WL33xx supports three main operating modes:

•

Run mode

•

Deepstop mode

•

Shutdown mode

The transition from one mode to another one is managed through a PMU state machine.

3.6.1

Run mode

In Run mode, the STM32WL33xx is fully operational.

In Run mode:

•

both regulators (MLDO and LPREG) are enabled

•

the MLDO provides the power supply for both VDD12i and VDD12o

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 14/91

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