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GC5322 FUNCTIONAL BLOCK DIAGRAM

IPDL

Detect

BBin

FB

TX

(LVDS)

18Pairs

(LVDS)

19Pairs

Gain

Pilot

Insertion

AntCal

Insertion

Power

Meter

16

BBFR

MFIO[19:18]

2

(Optional;

additional

2LSBs)

Wide

Band

DUC

Wide

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

NarrowBandDUC

+

CFR

Fractional

Farrow

Resampler

Circular

Limiter

GC5322

JTAG

MPUInterface

RESETB SYNC

3

SYNC

OUT

TCK

TRSTB

TDI

TMS

TDO

16

10

4

BBCLK

DPDCLK

SYNCD

(LVDS)

(LVDS)

BB

PLL

DPD

PLL

RealtoComplex

(orBypass)

Feedback

Equalizer

FeedbackNL

Correction

BulkInterpolation

+Mixer

Transmit

Equalizer

DPD

ADC

Interface

DAC

Interface

CaptureBuffers

DUCsin

1-ChnMode

DUCsin

2-ChnMode

DUCsin

6-ChnMode

BBClockDomain

DPDClockDomain

B0279-01

GC5322

SLWS208 – JANUARY 2008

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

352-ball S-PBGA package, 27 mm

× 27 mm

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

2

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Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): GC5322