STA381BWS datasheet(144/174 Pages) STMICROELECTRONICS

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STA381BWS

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DocID018937 Rev 7

7.13

Fault-detect recovery constant registers (addr 0x2B - 0x2C)

The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted,

the TRISTATE output is immediately asserted low and held low for the time period specified

by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x300C gives approximately 1 sec.

0x0000 is a reserved value.

7.14

Device status register (addr 0x2D)

This read-only register provides fault and thermal-warning status information from the power

control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault

or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

7.15

EQ coefficients configuration register (addr 0x31)

The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is

not active. In this case, the high-pass crossover filter works as a pass-through on the data

path (b=0, all the other coefficients at logic 0 ) while the low-pass filter is configured to have

zero signal on channel 3 data processing (all the coefficients are at logic 0).

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

00110000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

00001100

PLLUL

FAULT

Reserved

Table 153. Status register bits

Bit

R/W

RST

Name

Description

PLLUL

0: PLL locked

1: PLL not locked

FAULT

0: fault detected on power bridge

1: normal operation

XOB

Reserved

00000000

Obsolete

Product(s)

- Obsolete

Product(s)

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