 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
AMC7836IPAP bảng dữ liệu(PDF) 70 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AMC7836IPAP bảng dữ liệu(HTML) 70 Page - Texas Instruments |
|
|
70 / 91 page  70 AMC7836 SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018 www.ti.com Product Folder Links: AMC7836 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated 7.6.13.4 Power-Down 1 Register (address = 0xB3) [reset = 0x00] Figure 112. Power-Down 1 Register (R/W) 7 6 5 4 3 2 1 0 PDAC-D15 PDAC-D14 PDAC-D13 PDAC-D12 PDAC-C11 PDAC-C10 PDAC-C9 PDAC-C8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 60. Power-Down 1 Register Field Descriptions Bit Field Type Reset Description 7 PDAC-D15 R/W 0 After power-on or reset, all bits in the power-down register are cleared to 0, and all the components controlled by this register are either powered-down or off. The power-down register allows the host to manage the AMC7836 power dissipation. When not required, any of the DACs can be put into clamp mode and the ADC and internal reference into an inactive low-power mode to reduce current drain from the supply. The bits in the power-down register control this power-down function. Set the respective bit to 1 to activate the corresponding function. 6 PDAC-D14 R/W 0 5 PDAC-D13 R/W 0 4 PDAC-D12 R/W 0 3 PDAC-C11 R/W 0 2 PDAC-C10 R/W 0 1 PDAC-C9 R/W 0 0 PDAC-C8 R/W 0 7.6.13.5 Power-Down 2 Register (address = 0xB4) [reset = 0x00] Figure 113. Power-Down 2 Register (R/W) 7 6 5 4 3 2 1 0 Reserved PREF PADC R/W-All zeros R/W-0 R/W-0 Table 61. Power-Down 2 Register Field Descriptions Bit Field Type Reset Description 7-2 Reserved R/W All zeros Reserved for factory use. 1 PREF R/W 0 After power-on or reset, all bits in the power-down register are cleared to 0, and all the components controlled by this register are either powered-down or off. The power-down register allows the host to manage the AMC7836 power dissipation. When not required, any of the DACs can be put into clamp mode and the ADC and internal reference into an inactive low-power mode to reduce current drain from the supply. The bits in the power-down register control this power-down function. Set the respective bit to 1 to activate the corresponding function. 0 PADC R/W 0 |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
