MB85RC256VPNF-G-AMERE2 datasheet(2/39 Pages) RAMXEED

2 / 39 page

MB85RC256V

DS501-00017-11v2-E



PIN ASSIGNMENT



PIN FUNCTIONAL DESCRIPTIONS

Number

Pin Name

Functional Description

1 to 3

A0 to A2

Device Address pins

The MB85RC256V can be connected to the same data bus up to 8 devices.

Device addresses are used in order to identify each of these devices. Connect

these pins to VDD pin or VSS pin externally. Only if the combination of VDD and

VSS pins matches Device Address Code inputted from the SDA pin, the device

operates. In the open pin state, A0, A1 and A2 pins are internally pulled-down

and recognized as the "L" level.

VSS

Ground pin

SDA

Serial Data I/O pin

This is an I/O pin which performs bidirectional communication for both memory

address and writing/reading data. It is possible to connect multiple devices. It is

an open drain output, so a pull-up resistor is required to be connected to the ex-

ternal circuit.

SCL

Serial Clock pin

This is a clock input pin for input/output serial data. Data is sampled on the ris-

ing edge of the clock and output on the falling edge.

Write Protect pin

When the Write Protect pin is the “H” level, the writing operation is disabled.

When the Write Protect pin is the “L” level, the entire memory region can be

overwritten. The reading operation is always enabled regardless of the Write

Protect pin input level. The Write Protect pin is internally pulled down to VSS

pin, and that is recognized as the “L” level (write enabled) when the pin is the

open state.

VDD

Supply Voltage pin

VSS

VDD

SCL

SDA

VSS

VDD

SCL

SDA

(TOP VIEW)

(8-pin plastic SOP,150mil)

(TOP VIEW)

(8-pin plastic SOP, 208mil)

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