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MB85RC256TY bảng dữ liệu(PDF) 9 Page - RAMXEED LIMITED

tên linh kiện MB85RC256TY
Giải thích chi tiết về linh kiện  256K (32 K x 8) Bit I2C
PDF  39 Pages
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nhà sản xuất  RAMXEED [RAMXEED LIMITED]
Trang chủ  https://www.ramxeed.com/
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MB85RC256TY bảng dữ liệu(HTML) 9 Page - RAMXEED LIMITED

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MB85RC256TY(AEC-Q100 Compliant)
DS501-00077-1v1-E
9
• Sequential Read
Data can be received continuously following the Device address word (R/W “1” input) after specifying the
address in the same way as for Random Read. If the read reaches the end of address, the internal read
address automatically rolls over to first memory address (0000H) and keeps reading.
• High Speed Mode
MB85RC256TY supports High Speed mode up to 3.4 MHz. By sending an entry command (0000 1XXX)
after start condition from the master side, it informs to the slave that the data transmission with High Speed
mode will start.
Since there is no slave side which is allowed to respond to this entry command, NACK response continues
from the slave side. After the master side recognizes this NACK response, the master side changes its state
to High Speed mode and enables the bidirectional communication up to 3.4 MHz.
By sending Stop condition, it exits out of the state in High Speed communication.
Stop Condition
ACK (SDA is the "L" level)
A
P
NACK (SDA is the "H" level)
N
AA
A
N
P
Read
Data 8bits
Read
Data 8bits
Read
Data
...
...
Access from master
Access from slave
A
S
P
N
S
A2 A1
A
N P
Read
Data 8bits
1
1
010
S1
X
N
X
0
000
X
AA
A
N P
Read
Data 8bits
Read
Data 8bits
Read
Data
...
...
S
A2 A1
A
A
A
A P
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
0
10 1 0
S1
X
N
X
0
000
X
S
A2 A1
A
A
A
A
A P
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
Write
Data
0
...
10 1 0
S1 X
N
X
0
000
X
S
A2 A1
A
A
A
P
Address
High 8bits
Address
Low 8bits
0
10 1 0
S
A2 A1
A
1
1
010
Read
Data 8bits
N
S1
X
N
X
0
000
X
S
A2 A1
A
A
A
Address
High 8bits
Address
Low 8bits
0
10 1 0
S
A2 A1
A
1
1
010
Read
Data 8bits
A
S1
X
N
X
0
000
X
...
A
N
A0
A0
A0
A0
A0
A0
A0
Access from slave
Start Condition
Stop Condition
ACK(SDA is the “L” level)
NACK(SDA is the “H” level)
Byte Write @High Speed Mode
Page Write @High Speed Mode
Current Address Read @High Speed Mode
Random Address Read @High Speed Mode
Sequential Read @High Speed Mode
High Speed Mode
Standard Mode
Fast Mode
Fast Mode Plus
Access from master



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